The escalating requirements for density and performance associated with ultra large scale integration (ULSI) circuits require responsive changes in interconnection technology which is considered a very demanding aspect of ULSI technology. High density demands for ULSI integration require planarizing layers with minimal spacing between conductive lines.
Single damascene is a technique developed to address disadvantages (e.g., poor metal step coverage, residual metal shorts, low yields, uncertain reliability, and poor ULSI integration extendability) associated with traditional etch back methods. Damascene, an art which has been employed for centuries in the fabrication of jewelry, has been adapted for application in the semiconductor industry. Damascene basically involves the formation of a trench which is filled with a metal. Thus, damascene differs from traditional etch back methods which involve building up a metal wiring layer and filling the interwiring spaces with a dielectric material.
Single damascene techniques offer the advantage of improved planarization as compared to etch back methods; however, single damascene is time consuming in that numerous process steps are required. Undesirably, an interface exists between the conductive via and conductive wiring. Moreover, adequate planarization layers containing an interwiring spacing less than 0.35 .mu.m are difficult to achieve.
An improvement to single damascene is dual damascene which involves substantially simultaneous formation of a conductive via and conductive wiring. The dual damascene technique requires less manipulative steps than the single damascene technique and eliminates the interface between the conductive via and conductive wiring which is typically formed by the single damascene technique. In very and ultra large scale integration (VLSI and ULSI) circuits, an insulating or dielectric material, such as silicon oxide, of the semiconductor device in the dual damascene process is patterned with several thousand openings for the conductive lines and vias which are filled with metal, such as aluminum, and serve to interconnect active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming multilevel signal lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrate on which semiconductor devices are mounted.
A conventional dual damascene process includes covering an insulating layer with a photoresist material layer which is exposed to a first mask with an image pattern of via openings, and anisotropically etching the pattern in the upper half of the insulating layer. The patterned photoresist material layer is then removed and the insulating layer is coated with a second photoresist material layer which is exposed to an a second mask with an image pattern of trenches in alignment with the via openings. In anisotropically etching the trenches in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and trenches are filled with metal to form contacts and conductive lines. Although this standard dual damascene technique offers advantages over other processes for forming interconnections, it has a number of disadvantages, such as the edges of the via openings and the sidewalls of the via in the lower half of the insulating layer are poorly defined because of the two etchings and the via edges and sidewalls being unprotected during the second etching.
An improvement over the conventional dual damascene process is a process known as a back end integration or a trench first via last (TFVL) dual damascene process. In this process, the trenches are etched first and the vias are etched last. Although, this eliminates some of the problems with the poorly defined edges, the process creates other problems. For example, the etching of the trenches includes etching both small and large trenches. Small trenches have widths that are not much larger than the vias, while large trenches have widths much larger than the vias. During a via patterning step, portions of the photoresist material flows into the large trenches causing an non-uniform thickness over the large trenches. Due to the fact that the exposure of the photoresist material layer is very sensitive to the energy and the wavelength of the light source used to expose the photoresist material layer, the thicker portions of the photoresist material layer do not become fully exposed resulting in undesirable defects during the etching step. Using a higher energy for thicker resist and the remaining resist results in an unacceptable result.
In view of the above, improvements are needed to mitigate exposure defects associated with back end integration or TFVL dual damascene processes.